In modern hardware digital design, optimizing performance, resource utilization, and power consumption across different technological targets remains a critical challenge. Indeed, the drive for greater computational power, alongside the need to reduce power consumption, stems from a wide range of applications, from data centers to mobile devices. However, this push encounters significant cost barriers, as the manufacturing cost is closely tied to the technological nodes used and the area for integrated circuits, and is particularly influenced by the amount of available resources for FPGAs. These three criteria are inherently conflicting, as improving one often negatively impacts the others. Finding the best balance between these factors requires significant effort. To address these complexities, design automation tools are increasingly valuable. Odatix is an open-source toolbox designed for the automated implementation and validation of parametrizable digital architectures. It supports synthesis, placement and routing for various FPGA and ASIC tools and simulators. It simplifies key stages such as synthesis, place and route, simulation, and validation, allowing designers to efficiently navigate multiple configurations and identify optimal solutions tailored to specific application constraints. Indeed, Odatix enables comparative analysis of multiple architectural configurations through various metrics such as maximum operating frequency, resource utilization, and power consumption. This paper presents an overview of Odatix’s capabilities and its application to the AsteRISC processor, demonstrating its utility in choosing the best architectural configuration, technological target and EDA tool for specific application constraints.

Embedded systems typically require the transmission of significant amounts of data to small-scale CPUs for applications such as radar signal processing, image processing, and embedded AI. Ensuring data integrity during transmission is typically managed using Cyclic Redundancy Check (CRC) algorithms. However, achieving real-time CRC calculation and data storage poses challenges, often necessitating large FIFO memories and multiple clock domains. These additional resources involve a greater hardware complexity. This paper presents an approach aimed at synchronizing the CPU frequency with data transmission. This enables having a single clock domain and a reduction of power consumption. Using hardware/software co-design, it is possible to achieve real-time data storage and CRC calculation without data loss and with a low power consumption.

This paper addresses the need for customizable processor architectures by presenting the design and implementation, on both FPGA and ASIC devices, of a flexible RISC-V in-order pipeline core. The study expands the design space exploration possibilities by introducing a customizable number of stages in the pipeline architecture. The methodology leverages the fundamental building blocks of non-pipelined architectures while incorporating different interconnections and a specific control unit. Through evaluation and analysis, this study provides insights into the impact of pipeline architecture on performance, while also highlighting the advantages of non-pipeline processors in architecture design. The findings contribute to the field by enabling the identification of the optimal architecture, considering application constraints and target technology, in the domain of size-optimized and low-power CPUs.

The RISC-V open source instruction set architecture is a promising solution for applications related to low power embedded systems. This paper presents a configurable RISC-V processor architecture providing a compromise between the number of clock cycles required to execute an instruction, the maximum operating frequency, the resource utilization and the power consumption. This architectural flexibility enables the processor to be adapted to fit application constraints, on either FPGA or ASIC targets.